1. Field of the Invention
The present invention relates to flip flops and, more particularly, to a flip flop which has complementary, symmetric, minimal timing skew outputs.
2. Description of the Related Art
A flip flop is a device which latches the logic state of a data input signal when a predetermined edge of a clock input signal is detected. As a result, a flip flop generates a flop data output signal whose logic state matches the logic state of the data input signal when the predetermined edge of the clock input signal is detected. Additionally, flip flops typically contain a second data output signal whose logic state is the complement (logical inverse) of the first data output signal.
If a flip flop has true/complementary data outputs which are exact mirror images of each other in the time domain, these outputs are said to be complementary and symmetric. Therefore, the rise time of the true data output signal and the fall time of the complementary data output signal must be equal, and the fall time of the true data output signal and the rise time of the complementary data output signal must also be equal. As a result, the flop true/complementary data outputs must change state at exactly the same time, such that both of them will reach the power supply mid-point voltage at exactly the same time.
FIG. 1 shows a timing diagram which illustrates the operation of a flip flop that has complementary, symmetric outputs. As shown in FIG. 1, the flip flop generates a data output signal Q and a complementary data output signal QZ. In addition, the Q and QZ data outputs have equal rise and fall times (equal to two time units). Furthermore, the Q and QZ data outputs change state at exactly the same time, so that they reach the power supply mid-point voltage VDD/2 at exactly the same time.
Many applications require the use of flip flops which have complementary, symmetric outputs. High accuracy digital-to-analog converters (DACs) are an important example. High accuracy DACs are used in a wide variety of applications, including telecommunications, control systems and filters for digital signal processors.
FIG. 2 shows a schematic diagram which illustrates a conventional digital-to-analog interface 200 for one bit of a high-accuracy differential DAC. As shown in FIG. 2, interface 200 includes a flip flop FF1 which has a data input 210 that receives a data signal DATA, and a clock input 212 that receives a clock signal CLK. Flip flop FF1 also has complementary, symmetric outputs which include a data output 214 that generates a flop signal Q, and a complementary data output 216 that generates a complementary flop signal QZ.
Referring to FIG. 2, interface 200 also includes a pair of p-channel load transistors M1 and M2, a pair of differential input transistors M3 and M4, and a current source I. P-channel transistors Ml and M2 both have sources connected to a power supply voltage VDD. In addition, transistor M1 has a gate and a drain connected to a first output node N1, while transistor M2 has a gate and a drain connected to a second output node N2.
N-channel transistors M3 and M4 both have sources connected to current source I which, in turn, is connected to ground. In addition, transistor M3 has a gate connected to data output 214 and a drain connected to first output node N1, while transistor M4 has a gate connected to data output 216 and a drain connected to second output node N2. A differential output is taken across output nodes N1 and N2.
In order to maintain high DAC accuracy, the complementary flop output signals Q and QZ must be mirror images of each other in the time domain. In other words, their rise and fall times must be equal to each other, and they must change state at exactly the same time.
When these conditions are met, the rising and falling waveforms of Q and QZ will cross each other at exactly one half of the power supply voltage (VDD/2), thereby producing an undistorted differential output waveform at nodes N1 and N2.
FIG. 3 shows the schematic diagram of a prior art flip flop 300. Referring to FIG. 3, flop 300 has a clock inverter U1, a master latch 310, and a slave latch 312. Clock inverter U1 has an input connected to an external clock input 314 to receive a clock signal CLK, and an output which generates an inverted clock signal CPZ.
Master latch 310 includes a first transmission gate 316 and a second transmission gate 318. First transmission gate 316 includes an n-channel transistor M1 which has a drain connected to an external data input 320 to receive a data signal D, a source, and a gate connected to the output of clock inverter U1 to receive the inverted clock signal CPZ.
First transmission gate 316 also includes a p-channel transistor M2 which has a source connected to external data input 320 to receive the data signal D, a drain connected to the source of transistor M1, and a gate connected to external clock input 314 to receive the clock signal CLK.
Second transmission gate 318 includes an n-channel transistor M3 which has a drain, a source connected to the source of transistor M1, and a gate connected to external clock input 314 to receive the clock signal CLK. Second transmission gate 318 also includes a p-channel transistor M4 which has a source connected to the drain of transistor M3, a drain connected to the source of transistor M3, and a gate connected to the output of clock inverter U1 to receive the inverted clock signal CPZ.
In addition to first and second transmission gates 316 and 318, master latch 310 also includes an inverter U2 which has an input connected to the source of transistor M1, and an output which generates a latched signal QM. Master latch 310 additionally includes an inverter U3 which has an input connected to the output of inverter U2, and an output which is connected to the drain of transistor M3.
Slave latch 312 includes a third transmission gate 324 and a fourth transmission gate 326. Third transmission gate 324 includes an n-channel transistor M5 and a p-channel transistor M6. Transistor M5 has a drain connected to the output of inverter U2 to receive the latched signal QM, a source, and a gate connected to external clock input 314 to receive the clock signal CLK. Transistor M6 has a source connected to the output of inverter U2 to receive the latched signal QM, a drain connected to the source of transistor M5, and a gate connected to the output of clock inverter U1 to receive the inverted clock signal CPZ.
Fourth transmission gate 326 includes an n-channel transistor M7 which has a drain, a source connected to the source of transistor M5, and a gate connected to the output of clock inverter U1 to receive the inverted clock signal CPZ. Fourth transmission gate 326 also includes a p-channel transistor M8 which has a source connected to the drain of transistor M7, a drain connected to the source of transistor M7, and a gate connected to external clock input 314 to receive the clock signal CLK.
In addition to transmission gates 324 and 326, slave latch 312 also includes an inverter U4 and an inverter U5. Inverter U4 has an input connected to the source of transistor M5 and an output, while inverter U5 has an input connected to the output of inverter U4, and an output which generates the inverted flop signal QZ.
Slave latch 312 also includes an inverter U6 and an inverter U7. Inverter U6 has an input connected to the output of inverter U4, and an output connected to the drain of transistor M7. Inverter U7 has an input connected to the output of inverter U6, and an output which generates the flop data signal Q.
In operation, flop 300 attempts to generate complementary, symmetric outputs at Q and QZ by equalizing the propagation delay in two output signal paths. The first output signal path is from the input of inverter U4 to the output of inverter U5, ending with the inverted flop output signal QZ. The second output signal path is from the input of inverter U4, through inverters U6 and U7, ending with the flop output signal Q.
One problem with flop 300 is that the first output signal path contains two inverters (U4 and U5), while the second output signal path contains three inverters (U4, U6, and U7). Thus it is almost impossible to equalize the propagation delays of these two output signal paths over all process, voltage and temperature conditions (PVT conditions). The best that can be done is to equalize the path delays at one process corner, usually typical PVT, and then tolerate the delay changes, known as a timing skew, at the other process corners. Of course, this timing skew distorts the analog differential waveform between nodes N1 and N2 of interface 200.
FIG. 4 shows a timing diagram which illustrates the operation of a flip flop, such as flipflop 300, that has non-symmetric complementary outputs due to PVT induced timing skew.
Referring to FIG. 4, flip flop outputs Q and QZ are complementary outputs which have equal rise and fall times (equal to 2 time units). However, as shown in FIG. 4, data signal QZ changes state slightly before data signal Q (by one time unit), due to the previously described difference in path delay. Thus flip flop signals Q and QZ do not reach the power supply mid point voltage (VDD/2) at exactly the same time, resulting in signal asymmetry between Q and QZ. This signal asymmetry, due to timing skew, causes the differential analog output signal between nodes N1 and N2 in FIG. 2 to become distorted. This distortion is highly undesirable because it adversely affects the accuracy of the DAC analog output.
FIG. 5 shows the schematic diagram of a prior-art flip flop 500. Flop 500 illustrates a second implementation of flop FF1 in FIG. 2. Flop 500 is similar to flop 300 and, as a result, utilizes the same reference numerals to designate structures which are common to both flops. Referring to FIG. 5, Flop 500 differs from flop 300 in that flop 500 has a slave latch 510 which is different from slave latch 312.
As shown in FIG. 5, slave latch 510 contains several components which are also present, and identically connected, in slave latch 312. These components include transistors M5-M8 and inverters U4, U5 and U6.
Referring to FIG. 5, slave latch 512 includes a fifth transmission gate 528. Transmission gate 528 has an n-channel transistor M9 and a p-channel transistor M10. Transistor M9 has a drain connected to the input of inverter U6, a source which outputs the flop data signal Q, and a gate connected to external clock input 314 to receive the clock signal CLK. Transistor M10 has source connected to the drain of transistor M9, a drain connected to the source of transistor M9, and a gate connected to the output of clock inverter U1 to receive the inverted clock signal CPZ.
In operation, flop 500 attempts to obtain complementary, symmetric outputs by equalizing two propagation delays. The first propagation delay is from the output of inverter U4 to the output of inverter U5, ending with the inverted flop output signal QZ. The second propagation delay is from the output of inverter U4 to the output of transmission gate 528, ending with the flop output signal Q.
Although the delay through inverter U5 can be made equal to the delay through transmission gate 528 at one process corner, (usually typical PVT), the difference between these two delays will definitely change at other process corners.
Furthermore, the output impedance driving the inverse flop signal QZ is due to inverter U5, whereas the output impedance driving the flop signal Q is due to inverter U4 in series with transmission gate 528. Since it is virtually impossible to perfectly balance these two impedances under all PVT conditions, the differential analog waveform between nodes N1 and N2 of interface 200 will become distorted when non-typical PVT conditions are present.
As a result, there is a definite need for a flip flop which has complementary, symmetric outputs that have substantially zero timing skew, under all PVT conditions.
The flip flop of the present invention provides complementary, symmetric outputs which have substantially zero timing skew over all process, voltage and temperature conditions (PVT conditions). This is accomplished by utilizing a master latch to output a latched signal and an inverted latched signal, and a pair of slave latches to synchronize the latched signal and the inverted latched signal to the rising edge of the clock signal.
A flip flop in accordance with the present invention includes a first device which has a first input that receives a clock signal and a second input that receives a data signal. The first device also includes a first output which generates a first output signal, and a second output which generates an inverted first output signal. The clock signal alternates between a first logic state and a second logic state. The first device generates the first output signal with a logic state in response to the data signal when the clock signal is in the first logic state, and holds the logic state of the first output signal when the clock signal is in the second logic state. The first output signal is held by the first device in the state which was present when the clock signal transitioned from its first logic state to its second logic state.
The flip flop also includes a second device which has a third input that receives the clock signal, and a fourth input that receives the first output signal. The second device has a third output which generates a second output signal. The second device generates the second output signal with a logic state in response to the first output signal when the clock signal is in the second logic state, and holds the logic state of the second output signal when the clock signal is in the first logic state. The second output signal is held by the second device in the state which was present when the clock signal transitioned from its second logic state to its first logic state.
Furthermore, the flip flop also includes a third device which has a fifth input that receives the clock signal, and a sixth input that receives the inverted first output signal. The third device has a fourth output which generates an inverted second output signal. The third device generates the inverted second output signal with a logic state in response to the inverted first output signal when the clock signal is in the second logic state, and holds the logic state of the inverted second output signal when the clock signal is in the first logic state. The inverted second output signal is held by the third device to the state which was present when the clock signal transitioned from its second logic state to its first logic state.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.